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Multiplex Interface Selection Circuit

IP.com Disclosure Number: IPCOM000096093D
Original Publication Date: 1964-Dec-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

O'Connor, LT: AUTHOR

Abstract

Circuit 10 permits rapid propagation of a CPU generated serial polling signal through I/O devices not requiring service.

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Multiplex Interface Selection Circuit

Circuit 10 permits rapid propagation of a CPU generated serial polling signal through I/O devices not requiring service.

To sequentially poll a plurality of remote I/O devices, the central processing unit raises the line level into 10 of remote I/O 1 which immediately passes this line level to a similar circuit 10 in I/O 2 if no service is requested for I/O 1. If I/O 1 requires service, the passage of the line level to I/O 2 is blocked and I/O 1 establishes communication with CPU. Return of the line level to CPU from 10 of I/O N indicates completion of polling.

Circuit 10 of each I/O employs And Inverts 12, 15, 16 and 17. Each of these produces a negative output if all inputs are positive or a positive output if any or all inputs are negative. Terminal 11 is connected to the CPU or preceding I/O device and is at a negative level in the absence of a polling signal which causes the output of 12 and 16 to be positive. A negative level at 14 would indicate a service,request generated by the I/O but 14 is otherwise positive providing the other conditioning input for AI 15. Thus, a negative output is produced by 15 causing a positive output for 17 and conditioning one input to driver 18. A positive polling signal at 11 would immediately actuate driver 18 and produce a positive level at output 20 for the next I/O or for return to the CPU with the delay in relaying the level being restricted to the recovery time of 18.

A negative ser...