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Browse Prior Art Database

Shift Register

IP.com Disclosure Number: IPCOM000096098D
Original Publication Date: 1964-Dec-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Zeman, RF: AUTHOR

Abstract

Data is entered into shift register 10 via input terminal 11. Each position of register 10 includes an information bit latch 13 and a storage latch 18. Entry of data into latches 13 and 18 is controlled by And's 12 and 16. At Adv 1 time each And 12 is conditioned to pass data. Store latches 18 are reset at Reset 2 time and data is transferred from latches 13 to 18 at Adv 2 time. Latches 13 are then reset at Reset 1 time.

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Shift Register

Data is entered into shift register 10 via input terminal 11. Each position of register 10 includes an information bit latch 13 and a storage latch 18. Entry of data into latches 13 and 18 is controlled by And's 12 and 16. At Adv 1 time each And 12 is conditioned to pass data. Store latches 18 are reset at Reset 2 time and data is transferred from latches 13 to 18 at Adv 2 time. Latches 13 are then reset at Reset 1 time.

Register 10 is without a store latch for the last position. However, if desired, a store latch can be included and its set output could be combined by means of an Or, not shown, with the data input line to form a recirculating register.

Register 10 is capable of high-speed operation. Noise spikes do not cause the addition or loss of bits.

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