Browse Prior Art Database

Read Only Memory

IP.com Disclosure Number: IPCOM000096161D
Original Publication Date: 1963-Jan-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Owen, CE: AUTHOR [+2]

Abstract

This memory structure is a balanced type in which there are two-input differential amplifiers, one amplifier for each bit of a word to be read out. The amplifiers are pulsed on one or the other input depending upon the presence of a 1 or a 0 in the associated bit of a stored word being read out. Any noise or readout pulse coupling through the storage of non-selected words is applied equally to both amplifier inputs and does not affect the memory output.

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Read Only Memory

This memory structure is a balanced type in which there are two-input differential amplifiers, one amplifier for each bit of a word to be read out. The amplifiers are pulsed on one or the other input depending upon the presence of a 1 or a 0 in the associated bit of a stored word being read out. Any noise or readout pulse coupling through the storage of non-selected words is applied equally to both amplifier inputs and does not affect the memory output.

A differential amplifier 10 is provided for each bit in the words to be stored. Each amplifier has two input leads 11 and 12. It responds to a difference in signals applied to leads 11 and 12. Crossing leads 11 and 12 are other leads 13 and 14, one pair for each word to be stored. Leads 13 and 14 are each connected through resistor 15 to the collector of transistor 16. This collector connects through resistor 17 to source +V. The transistor 17 emitter is grounded. Lead 13 of each word pair has a series diode 18 whose anode and lead 14 connect to ground through some terminating impedance. The anode of one diode 18 is pulsed when it is desired to read out the corresponding word.

To store a 1 at any word position, condenser 19 is connected between leads 12 and 13. A similar condenser is connected between leads 11 and 14. For storing a 0, the order of connections is reversed so that the condensers are connected at the opposite lead intersections, i. e., between 11 and 13 and between 12 and 14.

In oper...