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Common Bit Positions for Two Addresses

IP.com Disclosure Number: IPCOM000096179D
Original Publication Date: 1963-Jan-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Loser, EG: AUTHOR

Abstract

This buffer system includes a memory 18 which is divided into two equal halves. These store data words and corresponding control words. Each data word and its corresponding control word are stored at separate but related address locations. Certain bit positions of both words are commonly shared. With this arrangement, predetermined conditions are stored and retrieved when either word is being processed.

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Common Bit Positions for Two Addresses

This buffer system includes a memory 18 which is divided into two equal halves. These store data words and corresponding control words. Each data word and its corresponding control word are stored at separate but related address locations. Certain bit positions of both words are commonly shared. With this arrangement, predetermined conditions are stored and retrieved when either word is being processed.

Memory 18 operates as a standard coincident current magnetic core storage device. It has a memory cycle including a read portion and a write portion. Buffer memory addresses are selected from either the control word address portion of control word register 4 or I/O address register 10. Outputs of registers 4 or 10 are gated via address control gate 12 through decoder 14 to select X and Y drivers 16. Thus, during the read portion of the memory cycle, half-select drive signals are applied to selected X and Y drive lines. This causes the selected word to be read out of memory 18, to be sensed by sense amplifiers 20 and stored in buffer register 22. Logic operations are then performed on the information. During the write portion of the memory cycle, half-select signals are applied to selected X and Y drive lines. Such select the location at which the processed information is to be stored under control of inhibit drivers 28. Drivers 28 are selectively controlled by regeneration control unit 26, data control unit 24, data word register 2 via data word gates 6 and control word register 4 via control word gates 8.

Memory 18 is similar to standard three-dimensional coinciden...