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Reliability Regimen for Memory having Unswitchable Bits

IP.com Disclosure Number: IPCOM000096180D
Original Publication Date: 1963-Jan-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 41K

Publishing Venue

IBM

Related People

Anderson, JL: AUTHOR

Abstract

Memories having unswitchably defective bit positions operate reliably under a regimen which references the bits of a selected word to good bit positions only, ignoring defective bit positions.

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Reliability Regimen for Memory having Unswitchable Bits

Memories having unswitchably defective bit positions operate reliably under a regimen which references the bits of a selected word to good bit positions only, ignoring defective bit positions.

Each memory word storage location is provided with a number of extra bit positions sufficient to replace all defective bit positions. The function of the reliability regimen is to identify the defective bits and, in response to this identification, to alter the storage referencing so that defective bit positions are ignored. Each such bit position of the referenced word controls shifting of referencing so that all lower order bits shift one position. Provision for multiple defective bits involves a level of shifting for each such bit capacity.

Modern batch fabrication techniques for producing memory planes, considered advantageous in performance and cost, are likely to involve a finite low percentage of defective bits. Repairs are difficult to make. The drawing shows an eight-bit word storage location in memory which includes an unswitchable /1/ and an unswitchable /0/. These bit positions are useless and render an entire section of memory useless without some reliability provision. Write Operation.

In a write operation, an automatic loading of all 1's into the selected word storage location takes place. This is followed by an automatic read of the word into the output register. The register contents are complemented and a second read is done without clearing the output register. Defective bits /1/ and /0/ result in 1's in the output (out) register. These result from the first 0 (complemented into 1) and a 1 from the second read. The out register then contains 1's from the /0/ bit position and from the /1/ bit position. Both 1's in the out register denote defective bit positions in the word storage location.

The in register by this time has had the new data for word W inserted in its high order bit positions. The content of the out register is used to wedge 0's into the positions of the in register corresponding to the 1's in the out register. No...