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Binary Trigger Circuit

IP.com Disclosure Number: IPCOM000096190D
Original Publication Date: 1963-Jan-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 30K

Publishing Venue

IBM

Related People

Litwiller, RJ: AUTHOR

Abstract

In this transistorized binary trigger circuit, a single input line operates the trigger. Another single line is used to reset and hold the trigger to the off condition, regardless of the signals on the binary input line. The operating function is performed by split level, third level and normal current switching levels.

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Binary Trigger Circuit

In this transistorized binary trigger circuit, a single input line operates the trigger. Another single line is used to reset and hold the trigger to the off condition, regardless of the signals on the binary input line. The operating function is performed by split level, third level and normal current switching levels.

The circuit has a latch 1 including current switching Or 2 having a split level input S and a current switching And 3 having a third level input 4. Trigger circuit 5 includes Or 6 having a split level input and And 7 cross-coupled with it. The latch and trigger circuits are cross coupled via lines 8 and 9.

The reset source 10 is connected to And 7 via line 11. Output signals are available at terminals 12 and 13 (in-phase) and terminals 14 and 15 (out-of- phase).

The trigger is turned on and turned off by +N pulses on input line. 16. A -N pulse, brought in on the reset line 11, is used to reset the trigger off. The off condition is that when the in-phase output terminals 12 and 13 are in the down condition.

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