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Core Coupled Esaki Diode Memory

IP.com Disclosure Number: IPCOM000096191D
Original Publication Date: 1963-Jan-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Pricer, WD: AUTHOR [+2]

Abstract

This memory circuit operates at speeds of the order of 100 nanoseconds, has reduced current requirements, low noise signals and uses transistorized power supplies and drivers.

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Core Coupled Esaki Diode Memory

This memory circuit operates at speeds of the order of 100 nanoseconds, has reduced current requirements, low noise signals and uses transistorized power supplies and drivers.

Each memory circuit has a tunnel diode 1, a load resistor 2 and a transformer winding 3. The circuits are arranged in a matrix configuration. Each circuit is coupled to an X driver 5 through transformer windings 3 and 4 and serially connected to a Y driver 6.

All circuits connected to common X and Y drivers are in series. This reduces the power requirement of the drivers and renders the memory compatible with transistorized power supplies.

Each Y driver supplies current to juxtaposed lines of the matrix. Sense amplifier 7 is connected between each set of juxtaposed lines. Output signals at amplifier 7 are substantially undisturbed since noise signals developed on each line cancel at amplifiers 7. The transformer winding of each circuit differentiates the X unipolar pulse into negative and positive portions. The negative portion clears the tunnel diode, the positive portion, in combination with a positive pulse on the Y line to the circuit, sets the tunnel diode.

Alternatively, the circuit can be coupled to X and Y drivers and biased from a separate current source. Sensing of memory circuits can occur on either a bias line or through a transformer coupled X or Y line

Substituting a backward diode for the load resistor, 2 improves the operating margins of the c...