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System Organization of a Data Transmission Exchange

IP.com Disclosure Number: IPCOM000096227D
Original Publication Date: 1963-Feb-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 4 page(s) / 64K

Publishing Venue

IBM

Related People

Saxenmeyer, GJ: AUTHOR

Abstract

This is a Data Transmission Exchange DTE. The main storage in DTE is a 100 x 100 x 8 ferrite core array. It is addressable by character, by any four consecutive characters or by defined record. The storage capacity is 10, 000 characters, individually addressable by a four-digit decimal number. The regeneration loop contains sense amplifiers, two cascaded buffer registers, and inhibit drivers. Working address registers hold Program Address PAR, Data Address DAR, Compare Address CAR and the Overlap Address OAR. These registers are loaded serially from Storage by various program control functions via the 4/8-to-2/5 section of Common Code Translator CCT. As addresses are used, by transferring them one at a time to Storage Address Register SAR, they are serially incremented as they pass through Modifier MOD.

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System Organization of a Data Transmission Exchange

This is a Data Transmission Exchange DTE. The main storage in DTE is a 100 x 100 x 8 ferrite core array. It is addressable by character, by any four consecutive characters or by defined record. The storage capacity is 10, 000 characters, individually addressable by a four-digit decimal number. The regeneration loop contains sense amplifiers, two cascaded buffer registers, and inhibit drivers. Working address registers hold Program Address PAR, Data Address DAR, Compare Address CAR and the Overlap Address OAR. These registers are loaded serially from Storage by various program control functions via the 4/8-to-2/5 section of Common Code Translator CCT. As addresses are used, by transferring them one at a time to Storage Address Register SAR, they are serially incremented as they pass through Modifier MOD. The SAR output is translated to decimal value to provide four-dimensional address selection in the core array drive circuits. A validity check monitors the MOD output to detect erroneous addresses as they are used. The error signal triggers the automatic error controls required to maintain the program progression.

The CCT is the central control function of the DTE. It translates transmittal information to and from any and all line codes. The first CCT section converts between the 4/8 code used in storage and the wedge code used by the console typewriter. The second section translates the ten numerical characters, in 4/8 code, to the next higher numeric value. It is used to increment the data addresses of adapter service instructions, in effect utilizing the stored instruction as its own independent address register. In effect, each adapter has its own separate address register in storage. This requires that the program must, as part of the end-of-message processing routine, restore the data address of the particular adapter service instruction to its initial value for the next message. The next five CCT sections handle the line codes. The eighth section is BCD, which services the local I/O devices, such as magnetic tape, drum or disk file. The ninth section is the Operation Decoder, which translates the operation code into a three digit, 2/5-coded decimal number plus one of three additional mode indicators, a total of 18 bits. The hundreds-digit of the number specifies one of the ten functional types of instruction which DTE is capable of executing. The tens and units digits form a decimal code which specifies the particular operation defined by the Operation Code. The tenth section is the Compare Code translator, which converts the 64 data characters into their bipolar, 6-bit binary equivalents, in true collating sequence. The eleventh section is the 4/8 - 2/5 address translator, which converts numerical 4/8 characters to 2/5 code for the address registers.

The only program controls shown are Emitter EMTR, in parallel with the output to Storage of the Buffer Register, and Analyze...