Browse Prior Art Database

Counter

IP.com Disclosure Number: IPCOM000096278D
Original Publication Date: 1963-Mar-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 31K

Publishing Venue

IBM

Related People

Gersbach, JE: AUTHOR [+2]

Abstract

A random number or non-sequential output is realized by the counter in response to a binary input. The particular output sequence is determined by an instruction provided to the counter. This remains fixed for that sequence.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 62% of the total text.

Page 1 of 2

Counter

A random number or non-sequential output is realized by the counter in response to a binary input. The particular output sequence is determined by an instruction provided to the counter. This remains fixed for that sequence.

A stepping counter circuit of n + 1 stages is used for a counting sequence of 2/n/ numbers. Two sets of Exclusive-Or (OE) circuits of n stages each are employed with the counter circuit. Each of the circuits of the first set receives one digit of the instruction as one of its inputs, e. g., OE1, OE2 and OE3, receiving the 1, 2 and 4 inputs respectively. The output of the first stage of the counter circuit is coupled back as the second input to OE1, OE2 and OE3 to complement the instruction supplied to these circuits.

The second set of Exclusive-Or circuits, OE4, OE5 and OE6 receives the respective outputs of OE 1, OE2 and OE3 as one input. The second input for each of these circuits is provided from respective outputs of the counter stages after the first stage. Thus, stage 2 of the counter circuit is coupled to OE6, stage 3 to OE5 and stage 4 to OE4.

Since the first stage of the counter changes with each counter cycle the outputs from OE1, OE2 and OE3 are complemented on each cycle. These outputs, in turn, complement the outputs of OE4, OE5 and OE6 on each counter cycle. Therefore, if the particular instruction applied to OE1, OE2 and OE3 is chosen to be zero, and a binary input has not been supplied to the first stage of the counter...