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Data Compactor for Time Multiplexed Sensors

IP.com Disclosure Number: IPCOM000096282D
Original Publication Date: 1963-Mar-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 46K

Publishing Venue

IBM

Related People

Blasbalg, H: AUTHOR [+2]

Abstract

The multichannel compressor is efficient where the number of channels is large and where sensor signals exhibit a time structure, constant for relatively long periods of time, which signals change rapidly for substantially shorter periods of time. Sensor channels 10 for sensors S1... Sy are fed into PCM multiplexer 12 whose output is fed to an analog-to-digital converter 14. Its output drives modulo-2 adder 16 and Or 18.

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Data Compactor for Time Multiplexed Sensors

The multichannel compressor is efficient where the number of channels is large and where sensor signals exhibit a time structure, constant for relatively long periods of time, which signals change rapidly for substantially shorter periods of time. Sensor channels 10 for sensors S1... Sy are fed into PCM multiplexer 12 whose output is fed to an analog-to-digital converter 14. Its output drives modulo-2 adder 16 and Or 18.

The output of 16 drives the set input of No Change Latch 19 whose on output feeds one leg of And 20. Its output feeds one leg of Or 22. Its output drives the set input of Transmit Data Latch 24 whose on Output drives one leg of And 28. The And 28 output 30 is fed to a transmitter for transmission to a remote point. The output of Or 18 feeds the input to delay line 32 whose output 34 feeds the other input of adder 16. Tapped output 36 of delay 32 feeds the other leg of And
28. A timing and control circuit 38 has outputs 40... 50. These, respectively drive multiplexer 12, latch 19, And 20, Or 22, latch 24 and Or 18.

Multiplexer 12 scans inputs 10 sequentially. The multiplexer 12 output is digitized by converter 14 and is fed sequentially through Or 18 to delay 32. Circuits 38 produce a frame sync signal followed by a sensor 1 identification (ID) signal on line 50. This is prior to the arrival of data bits B11... B16 which represent bits from sensor 1. In the example, three bit positions are utilized for the frame sync and three are used for sensor identification. The value for each sensor Occupies six bit positions represented by B11... B16.

The length of delay 32 is such that it contains one entire frame. i. e., a frame sync plus identification bits, plus the bits B1... B6 for each sensor. In operation, latch 19 is initially set on so as to energize And 20. A timing pulse on line 42 samples And 20 to turn on latch 24. Such gates information from delay tap 36, through And 28 to output line 30. Thus, all sensor values for the first frame or scan of sensor inputs are transmitted. At the end of the first frame a timing pulse on line 41 resets latch 19 and a timing pulse on line 44 resets the latch 24. Latch 19 is continually reset by a pulse on line 41 after each bit from delay 32 is compared in adder 16. When the previous value for sensor 1 appears at output 34 of delay 32, the present value of sensor 1 appears at the output of converter
14. The two...