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Double Dimensional Accessing for Magnetic Core Storage System

IP.com Disclosure Number: IPCOM000096293D
Original Publication Date: 1963-Mar-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Kirkpatrick, TI: AUTHOR

Abstract

The core storage system assembles serial-by-bit data words from multiple channels operating in parallel. The data words are written into the array so that they can be read out parallel-by-bit.

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Double Dimensional Accessing for Magnetic Core Storage System

The core storage system assembles serial-by-bit data words from multiple channels operating in parallel. The data words are written into the array so that they can be read out parallel-by-bit.

The basic storage array has a plurality of stacked bit planes 10-1 ... 10-n, eachthreaded with its own Z winding. A plurality of X row windings thread all bit planes. A plurality of Y row windings thread all bit planes. All X-row windings are arranged in planes at 90 Degrees with respect to all Y row windings. All X and Y row winding planes are vertical with respect to the Z plane. To assemble the serial data arriving on lines 18-1... 18-n, an X winding is energized by driver 12 with half-select current. All Z windings except 16-1 are initially energized by drivers-16-1... 16-n. Each Y winding is connected to one of drivers 14-1... 14-n. These drivers energize the associated winding only if the corresponding bit arriving on lines 18-1... 18-n-is a 1. During subsequent bit times, Z drivers 16-2... 16-n are sequentially nonselected to permit the input bits arriving at that time to be written into into planes 10-2... 10-n in sequence so that the serial-by-bit words are assembled in the array.

Readout of a single assembled word is accomplished by selecting driver 12 and one of drivers 14-1... 14-n with all ' drivers nonselected. This operation permits the readout of the word, addressed by MAR, in a parallel-by-bit fa...