Browse Prior Art Database

Data Transfer and Conversion Circuit

IP.com Disclosure Number: IPCOM000096303D
Original Publication Date: 1963-Mar-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Crawford, JK: AUTHOR [+2]

Abstract

The byte converter enables character groups to be changed from one format to another using a minimum number of storage positions. A storage unit 101 handles data expressed in 6-bit bytes, BA 8421, and a data processor 102 handles data in 8-bit bytes. Data from unit 101 is converted to 8-bit bytes in a mode 1 operation. Data from data processor 102 and other 8-bit sources is converted to 6-bit characters in a mode 2 operation. The number of storage positions required for any conversion operation is obtained from the formula X = A+B - LCD, where X is minimum number of storage positions required, A is size (bit length) of input byte, B is size (bit length) of output byte and LCD is least common denominator of A and B.

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Data Transfer and Conversion Circuit

The byte converter enables character groups to be changed from one format to another using a minimum number of storage positions. A storage unit 101 handles data expressed in 6-bit bytes, BA 8421, and a data processor 102 handles data in 8-bit bytes. Data from unit 101 is converted to 8-bit bytes in a mode 1 operation. Data from data processor 102 and other 8-bit sources is converted to 6-bit characters in a mode 2 operation. The number of storage positions required for any conversion operation is obtained from the formula X = A+B - LCD, where X is minimum number of storage positions required, A is size (bit length) of input byte, B is size (bit length) of output byte and LCD is least common denominator of A and B.

In Mode 1, 6-bit characters on bus 121 are transferred through an Input Data Register (IDR) 122 and Input Gates (IG) 124 to a Conversion Register (CR) 125. This has twelve storage positions T1-T12. Eight-bit bytes are gated out of CR 125 through Output Gates (OG) 126 to Output Data Register (ODR) 128 and over bus 129. Mode 2 is similar, except cept that 8-bit bytes are applied to IDR 122 on bus 130 and 6-bit characters are derived from ODR 128 on bus 131. A mode Trigger (MT)103 is placed in one or the other of two states to establish a Mode 1 or Mode 2 operation by lines 105 and 111.

Either conversion operation involves four major cycles of the appropriate Step Pulse Generator 106 or 112. Each cycle includes four sample times from a Sample Pulse Generator 114. Characters (Mode 1) or bytes (Mode 2) are gated into CR 125 at Sample 1 time under c...