Browse Prior Art Database

Logic Unit

IP.com Disclosure Number: IPCOM000096306D
Original Publication Date: 1963-Mar-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Meade, RM: AUTHOR

Abstract

This logic unit generates selective logical connectives on a bit-by-bit basis and effects variable radix addition with parallel carry handling.

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Logic Unit

This logic unit generates selective logical connectives on a bit-by-bit basis and effects variable radix addition with parallel carry handling.

The logic unit has binary adder 104 and trinary adder 105. An addend byte P from register 101 combines with an augend byte Q from register 102 according to a modulus byte M from register 103. Bytes P and O are presented in parallel to binary adder 104 and also to trinary adder 105. Byte M is presented to trinary adder 105 only. Trinary adder 105 selectively provides, under control of program unit 106, either a binary full sum of three operands P, Q and M, actually P + Q - M, P - Q + M, Q - P + M, or a bit-for-bit logical connective of bytes P and O. Connective parity generator 109 produces parity indications of the result of connective operations to F register 112. This is also provided with signals indicating the value of a comparison of input bytes P and Q from status indicator 108.

During variable radix addition, a gate control circuit 107, which is responsive to carry-out signals from the binary and trinary adders 104 and 105, selects the outputs from binary adder. This is in the case where there is the relation sum < radix. Gate 107 selects the outputs from the trinary adder where there is the relation sum >/= radix. Gates 110 and 111 pass the selected adder output to R register 113. Gate 114 allows byte P to pass directly to R register 113 when required. Trinary adder 105 has two stages, a first carry-sav...