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Microminiaturized Capacitor Fabrication

IP.com Disclosure Number: IPCOM000096310D
Original Publication Date: 1963-Mar-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Davis, EM: AUTHOR

Abstract

This capacitor is readily fabricated by an improved form factor and is adapted to have input electrodes on one surface. Sheet 20 of dielectric material, typically glass or ceramic, has a first surface 22 and second surface 24. Surface 22 is entirely coated with a metallic conductor 26. Surface 24 has a series of metallic conductors 28 and 30 arranged in row and columnar fashion. Conductors 30 are twice the size of conductors 28. The conductor patterns are made by silk screening or plating-etching techniques. Then, the dielectric sheet 20 is sliced along center lines 32 and 32', 34 and 34' to form individual chips 36. The form factor selected permits the entire substrate to be utilized with a minimum of waste.

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Microminiaturized Capacitor Fabrication

This capacitor is readily fabricated by an improved form factor and is adapted to have input electrodes on one surface. Sheet 20 of dielectric material, typically glass or ceramic, has a first surface 22 and second surface 24. Surface 22 is entirely coated with a metallic conductor 26. Surface 24 has a series of metallic conductors 28 and 30 arranged in row and columnar fashion. Conductors 30 are twice the size of conductors 28. The conductor patterns are made by silk screening or plating-etching techniques. Then, the dielectric sheet 20 is sliced along center lines 32 and 32', 34 and 34' to form individual chips 36. The form factor selected permits the entire substrate to be utilized with a minimum of waste.

Each chip, in the lower drawing, represents a pair of series capacitors comprising plates 26-28 and 26-30' where 30' represents one-half the area of conductor 30. The chip can be joined to a suitable substrate 38. Substrate 38 includes conductive lands 40, portions of which are covered with solder 42 for joining the capacitor to the substrate. The conductors 28 and 301 are disposed on the solder portions 42. Then, the substrate and capacitor are heated in an oven at an appropriate temperature to melt the solder and join the capacitor electrode to the conductive land. The planar terminal topology of the capacitor facilitates the connection of the device to the substrate.

A typical capacitor is of the order of 100 x 100...