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Synchronous Cascode Set Reset Trigger

IP.com Disclosure Number: IPCOM000096312D
Original Publication Date: 1963-Mar-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Hartman, FB: AUTHOR [+3]

Abstract

This circuit is a set-reset bistable trigger having a delay time from input to output in the order of two nanoseconds. It employs a cascode latch T5, T6 and T7 as the circuit storage element and tunnel diode pair D1 and D2 as a waveform shaping element. The waveform diagrams show the circuit's operation and also voltage waveforms for entry, set, reset and output pulses and current waveforms for transistors T1... T7 as they respond to the input voltages. The composite characteristic curve of diode pair D1 and D2 is shown at the left.

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Synchronous Cascode Set Reset Trigger

This circuit is a set-reset bistable trigger having a delay time from input to output in the order of two nanoseconds. It employs a cascode latch T5, T6 and T7 as the circuit storage element and tunnel diode pair D1 and D2 as a waveform shaping element. The waveform diagrams show the circuit's operation and also voltage waveforms for entry, set, reset and output pulses and current waveforms for transistors T1... T7 as they respond to the input voltages. The composite characteristic curve of diode pair D1 and D2 is shown at the left.

Initially, T1 is conductive and biases T2 for nonconduction. Thus, regardless of the set and reset voltage values, T3 and T4 cannot conduct. The T4 collector potential holds T5 in a conductive state. Assuming that the initial output voltage is high, the feedback through conductor 2 holds T6 conductive. This, in turn, renders T7 nonconductive, preventing any current flow through T5. With no current in either T5 or T3, load line 16 intersects the diode pair composite curve 18 at point 20 with a resultant high voltage output.

Upon the occurrence of an up voltage on the set input, T3 is rendered capable of conduction. However, the circuit takes no action until an entry pulse is received at time y. The entry pulse renders T1 nonconductive, allowing T2 and T3 to become conductive. A current drain away from diode pair D1 and D2 is established. This current drain is sufficient to cause the intersection po...