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Logic Circuit

IP.com Disclosure Number: IPCOM000096325D
Original Publication Date: 1963-Apr-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 55K

Publishing Venue

IBM

Related People

Riekert, RH: AUTHOR

Abstract

The logic circuit analyzes a conditional statement bounded by IF and THEN, e.g., IF A = B AND (D > G OR F C W) THEN. . . . The propositions A = B, D > G, and F

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Logic Circuit

The logic circuit analyzes a conditional statement bounded by IF and THEN, e.g., IF A = B AND (D > G OR F C W) THEN. . . . The propositions A = B, D >
G, and F </- W are the tests to be performed each of which has the value 0 (False) or 1 (True). The circuit progressively evaluates the logical statement without regression and skips the unnecessary tests.

Successive code characters are entered in decoder 1 via input unit 2. An IF character is detected by start unit 3 to begin the conditional mode of operation such that latch 4 is turned off and zero is placed in binary counter 5. Counter 5 is incremented or decremented by 1. Its capacity determines the maximum number of nested parentheses. The count cannot be less than zero, i.e., if the count is zero and 1 is subtracted from it, the count remains zero.

The test character A = B is then decoded and appears on any other character lead 6 where it is gated through And 7 to test unit 8 where the test is made. If the test is true, i.e., A does equal B, a signal is transmitted on lead 9 to switch latch 10 on. This, in turn, conditions And's 13 and 14 And's 13 and 14 are also conditioned by the zero condition of counter 5 as well as And's 11 and 12.

The next character AND is decoded and appears on lead 15 and is gated by And 13 maintaining latch 4 off. This continues to condition And 7. The next character which is a left parenthesis appears on lead 19 is gated through Or 21 and And 22 to input unit 2. This en...