Dismiss
InnovationQ will be updated on Sunday, Oct. 22, from 10am ET - noon. You may experience brief service interruptions during that time.
Browse Prior Art Database

Synchronized Counter

IP.com Disclosure Number: IPCOM000096364D
Original Publication Date: 1963-Apr-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 44K

Publishing Venue

IBM

Related People

Krygowski, M: AUTHOR [+2]

Abstract

The synchronized counter is used where serializing and deserializing of multiple bit data representing signals must be achieved. A plurality of triggers T2, T4, T6 and T8 is stepped by complementary clock signals C, provided that an arbitrary not- stop signal is present, indicating that stopping of the operation has not been indicated, under the further control of certain other ones of the triggers and an arbitrary control trigger T9. The output of each trigger is utilized by a corresponding pair of output And's 01...08 so as to divide the times created by the triggers T2...T8 into eight output signals, in sequence, together with a zero signal provided by an And 10.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 55% of the total text.

Page 1 of 2

Synchronized Counter

The synchronized counter is used where serializing and deserializing of multiple bit data representing signals must be achieved. A plurality of triggers T2, T4, T6 and T8 is stepped by complementary clock signals C, provided that an arbitrary not- stop signal is present, indicating that stopping of the operation has not been indicated, under the further control of certain other ones of the triggers and an arbitrary control trigger T9. The output of each trigger is utilized by a corresponding pair of output And's 01...08 so as to divide the times created by the triggers T2...T8 into eight output signals, in sequence, together with a zero signal provided by an And 10. Trigger T9 is utilized as a form of delay so as to prevent the disenergizing of lower numbered And's too rapidly as a result of the energizing of higher numbered triggers.

As shown, the triggers come on in sequence. They remain on until all are reset simultaneously by an arbitrary reset signal R. Contrarywise, each And is operative only for a short period of time within the sequence. For instance, when trigger T2 goes on, output And 01 generates a One output first, since it is gated by not-clock time, the same as is the input And 12. Then, not-clock time ends cutting off And 01 and clock time begins turning on And 02. When the trigger T2 turned on initially, it reset trigger T9 thus blocking its own input, but enabling the input And I4. Due to the transition time of T9, however, t...