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Digital Signal Synchronous Modulation Circuits

IP.com Disclosure Number: IPCOM000096378D
Original Publication Date: 1963-Apr-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 91K

Publishing Venue

IBM

Related People

Fang, YE: AUTHOR [+3]

Abstract

These circuits provide synchronous modulation of digital signals through the use of logic devices.

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Digital Signal Synchronous Modulation Circuits

These circuits provide synchronous modulation of digital signals through the use of logic devices.

In circuit (1), a binary data input signal D having a first level representing a 1 and a second level representing a 0 is applied to single pulse generator 10. Clock pulses C1 having a repetition rate equal to that of the data bit rate (Fd = 1/
d) of the input signal D are applied to Or 12. Delayed clock pulses C2 having a repetition rate equal to that of pulses C1 but delayed by about a one-half bit period are also applied to generator 10. Generator 10 produces output pulses E corresponding to the pulses C2 applied to generator 10 during the time intervals when a 0 signal is applied simultaneously to it. Pulses C1 and pulses E from generator 10 pass through Or 12 to produce at its output pulses F. Binary trigger 14, in response to the pulses F, produces at its output the square waves 01 which pass through a low pass filter 16. This has, in this case, a cut-off frequency of 1.3 to 1.5 times the data rate to provide the desired output pulses
02. It should be noted that final waveform 02 can be viewed as a frequency modulated signal of the original waveform D, where one frequency, representing one bit, is twice the other frequency, representing a second bit. Alternatively, the signal 02 can be viewed as a phase modulated signal. As such, waveform 02 is in suitable form for data transmission.

Circuit (2) is similar to the circuit (1), differing from it only in that the pulses C1 applied to Or 12 are provided at twice the repetition rate of the pulses C1 applied to Or 12 in circuit (1). Also, pulses C2 applied to generator 10 of circuit
(2) are delayed by about three-quarters of a bit period and the cut-off frequency of LP filter 16 is somewhat less than two times that of the circuit (1). If desired, pulses C2 can be delayed by about one-quarter of a bit period rather than three- quarters of a...