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Read Only Memory

IP.com Disclosure Number: IPCOM000096402D
Original Publication Date: 1963-May-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 49K

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This read-only memory has a plurality of storage positions time-sharing a single gating circuit.

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Read Only Memory

This read-only memory has a plurality of storage positions time-sharing a single gating circuit.

Read-only memory 20 uses elements of a punched or etched hole reactive matrix array as, for example, the type disclosed in IBM Technical Disclosure Bulletin, Volume 4, No. 6, November 1961, Pages 23 and 24. Memory 20 comprises word lines 22... 22n and sense lines
24... 24n where n is an integer representative of the last element in a group. A capacitor is formed between the sense line and word line at each punched hole, these lines being on opposite sides of the printed circuit board. The word lines are serially connected and coupled to gate 25. Gate 25 comprises transistor 26 which receives X drives and Y drives at emitter and base electrodes, respectively.

The simultaneous presence of X and Y signals turns on the gate to transmit a pulse along the serially connected word lines. A sense circuit 30 of a type mentioned in IBM Technical Disclosure Bulletin, Volume 3, No. 10 March 1961, Page 18, is connected to the sense line. Sense circuit 20 is strobed by a signal applied to strobe circuit

When the gate is turned on, the leading edge of the drive signal is differentiated by the coupling elements at the punched hole positions. Each time the leading edge passes a sense line junction where a coupling element is placed, a pulse appears on the sense line. The presence or absence of a coupling element at each sense line junction indicates whether a 1 or...