Browse Prior Art Database

Message Switching Computer

IP.com Disclosure Number: IPCOM000096405D
Original Publication Date: 1963-May-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 64K

Publishing Venue

IBM

Related People

Bush, GH: AUTHOR [+4]

Abstract

A computer can be adapted to assemble, and ultimately distribute, messages received on a large number of communications lines. Only assembly is described, distribution being similar.

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Message Switching Computer

A computer can be adapted to assemble, and ultimately distribute, messages received on a large number of communications lines. Only assembly is described, distribution being similar.

Though any type of computer can be used, one having a random access memory is shown. Five characters, each character usually having seven bits, are stored in any word location specified by an address supplied to the memory. Addresses are provided on an address bus from memory address register MAR. Data words are communicated between memory and a memory buffer register MBR through a data bus, when writing, and an out bus, when reading. Since a memory word location can contain address information, the out bus also connects to MAR. Transfers of words are possible only when gates are enabled by appropriate control signals C1, C2, C3, etc., from clock-timed control circuits. The operation of such circuits under instruction control is described in Arithmetic Operations in Digital Computers, by R. K. Richards, D. Van Nostrand Company, Inc. 1955, Chapter 1 1 on "Computer Organization and Control." The operations described here can be interleaved with other operations.

Buffer image locations in memory, each location corresponding to a different communication line position in a buffer register, are assigned for holding one character for each line. As bits are serially received on 300 lines, they are simultaneously assembled into 300 characters in the buffer register. A location selector operates a positioner and MAR in synchronism to transfer the contents of five buffer register character positions at a time to the corresponding five positions of the buffer image in the memory. The number of characters transferred is dictated by the size of data register DR. In this example, DR handles as many characters (five characters, 35 bits) as can be stored in one word location in memory.

Since the location selector regularly scans the buffer register and the buffer image at a rate much faster than the rate at which information arrives on the lines, the buffer image in memory accurately reflects the current state of character reception and assembly by the buffer register.

Memory locations in Tables I and II and in an assembly area are assigned to each discrete message being received by a line. It is necessary to assign words in these locations only to active lines, there usually being many inactive lines. Any Table I word can be assigned to any line by placing the address of the buffer image location corresponding to that line in the buffer address field of the desired Table I word. This Table I word can then be associated with any Table II word by pl...