Browse Prior Art Database

Phase Ambiguity Corrector

IP.com Disclosure Number: IPCOM000096408D
Original Publication Date: 1963-May-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Meyer, OF: AUTHOR

Abstract

The upper drawing shows a phasing circuit for the clock of a bi-phase data transmission system. The circuit insures that the clock pulses are properly phased with regard to the data signal. The circuit is in the receiver and utilizes the synchronizing signal of specified binary value transmitted prior to the data. The clock is that generated by a doubler, squarer and divider. The phasing circuit has an And on one input to the divider. Such is opened to the clock signal (one divider output) coincident with the synchronizing signal at the data output and the rectified squarer output signal as set up in a threshold-detecting one-shot.

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Phase Ambiguity Corrector

The upper drawing shows a phasing circuit for the clock of a bi-phase data transmission system. The circuit insures that the clock pulses are properly phased with regard to the data signal. The circuit is in the receiver and utilizes the synchronizing signal of specified binary value transmitted prior to the data. The clock is that generated by a doubler, squarer and divider. The phasing circuit has an And on one input to the divider. Such is opened to the clock signal (one divider output) coincident with the synchronizing signal at the data output and the rectified squarer output signal as set up in a threshold-detecting one- shot.

The lower drawing shows a circuit in which the utilization of both divider outputs gates the data signal or its complement according to the clock phase as sensed by the And.

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