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Sequential memory Organization

IP.com Disclosure Number: IPCOM000096411D
Original Publication Date: 1963-May-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 51K

Publishing Venue

IBM

Related People

Rozenberg, DP: AUTHOR [+2]

Abstract

In this memory organization, memory locations can be selected sequentially without external addressing. Switch cores a, b, c and d are members of the Y selection matrix and e, f and g are members of the X selection matrix. Switch cores 1... 12 are for instruction words 1... 12, respectively, which are desired to be read in numerical order. The line labeled Read Memory Switch Cores passes through all instruction cores. The line labeled Read Matrix Cores passes through all cores in the X and Y matrices.

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Sequential memory Organization

In this memory organization, memory locations can be selected sequentially without external addressing. Switch cores a, b, c and d are members of the Y selection matrix and e, f and g are members of the X selection matrix. Switch cores 1... 12 are for instruction words 1... 12, respectively, which are desired to be read in numerical order. The line labeled Read Memory Switch Cores passes through all instruction cores. The line labeled Read Matrix Cores passes through all cores in the X and Y matrices.

Assume switch cores a and e are the only switch cores which are in the 1 state in their respective matrices, with all others being in the 0 state. Switch cores 1... 12 are also in the 0 state at this time. When controls call for an instruction, a read pulse is applied to the Read Matrix Cores line causing a and e to be set to the 0 state. The currents produced by a and e being set to 0 are coincident at switch core 1 causing it to be set to the 1 state.

Shortly after switch core 1 is set to the 1 state, a read pulse is again applied to the Read Matrix Cores line. The partial write currents are coincident at switch cores b and f causing them to be set to the 1 state. Switch core 1 being set first to the 1 state and then to the 0 state supplies a doublet current to read the memory cores associated with switch core 1. After completion of this cycle, all switch cores are in the 0 state except b and f. When the next instruction is desired,...