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One Transistor, Exclusive Or Circuit

IP.com Disclosure Number: IPCOM000096425D
Original Publication Date: 1963-May-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Akmenkains, IG: AUTHOR

Abstract

In this Or, the Or function is produced by applying two input signals to the collector of a transistor by way of an Or and to the base of the transistor by way of an And. Drawing A shows a pair of input terminals X and Y connected to the collector of transistor 1 by way of positive Or 2 and resistor 3. Terminals X and Y also connect to the base of transistor 1 by way of positive And 4. It is assumed that the positive level of signals corresponds to a 1.

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One Transistor, Exclusive Or Circuit

In this Or, the Or function is produced by applying two input signals to the collector of a transistor by way of an Or and to the base of the transistor by way of an And. Drawing A shows a pair of input terminals X and Y connected to the collector of transistor 1 by way of positive Or 2 and resistor 3. Terminals X and Y also connect to the base of transistor 1 by way of positive And 4. It is assumed that the positive level of signals corresponds to a 1.

Ground signals at both X and Y apply ground potential to the collector of transistor 1 by way of Or 2 and resistor 3. Positive signals at both terminals X and Y turn transistor 1 on to apply ground potential to the collector. A ground signal at one input turns transistor 1 off, and a positive signal at the other input is applied to the collector by way of Or 2 and resistor 3.

The exclusive Or output of transistor 1 is applied to the input of the second exclusive Or comprising transistor la, Or 2a, And circuit 4a and collector coupling resistor 3a. A third input terminal Z is connected to Or 2a and And circuit 4a. The output of transistor 1a provides the logic function (XY + XY)Z + (XY + XY)Z.

The collector output of transistor la is applied to a powering circuit comprising emitter follower stage 6 and common base stage 7. The output is taken from collector terminal 8 of stage 7. Since there is a power loss in the exclusive Or states, the output signal from transistor 1a require...