Browse Prior Art Database

Mark Discrimination Circuit

IP.com Disclosure Number: IPCOM000096427D
Original Publication Date: 1963-May-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 60K

Publishing Venue

IBM

Related People

Bene, JF: AUTHOR [+3]

Abstract

This circuit indicates the darkest of a plurality of marks which exceed a preset minimum intensity. This is by repetitively sampling the concurrent outputs of photoelectric transducers each sensing a designated mark position.

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Mark Discrimination Circuit

This circuit indicates the darkest of a plurality of marks which exceed a preset minimum intensity. This is by repetitively sampling the concurrent outputs of photoelectric transducers each sensing a designated mark position.

In scanning a moving document, such as a student's answer sheet, all possible marking positions for one question are optically scanned repetitively to determine the position containing the darkest mark. A timing channel provides control pulses for the scanning channels, by sensing preprinted timing marks along the document edge, and also provides a threshold level for the scanning channels.

Channels 1... 5 each scan a mark position and the timing channel scans preprinted timing marks. The photoelectric sensing circuits of the channels are identical to that shown for channel 5. Each includes photoelectric transducer 7 in series with chopping transistor 8 controlled by a stage in timing ring 9. Each transducer generates current proportional to the quantity of light sensed. When gated on by transistor 8, each provides an input current signal to amplifier 12. Diode 13 is connected in parallel with transducer 7 and prevents large signal overshoots during gating.

Initially, the transducers of channels 1... 5 are adjusted to provide signals of identical amplitude from a standard reference background. To compensate for dirt and smudge on a document, the timing channel transducer is adjusted to provide a smaller amplitude signal. This establishes the minimum threshold that the remaining channels must exceed before any mark is recognized. The threshold value is stored by gating the amplified timing channel output into memory capacitor 14 through transistors 15 and 16 comprising a comparing circuit. Gating is controlled by transistor 17.

Normally, transistor 17 is on, holding transistors 15 and 16 off. When the threshold voltage is to be stored, transistor 17 is turned off by a signal on its base as the timing channel transducer is scanning blank document area. When transistor 17 turns off, the voltage level of junction 18 starts to rise permitting transistor 16 to conduct and charge capacitor 14. However, as junction 18 reaches a level sufficient that transistor 15 starts to conduct in response to the amplified timing channel signal, the junction fails to rise further so that transistor 16 turns off. Gating transistor 17 is then turned on. Thus, capacitor 14 has stored on it a charge representi...