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Fluid Logic Shift Register with Intermediate Stages

IP.com Disclosure Number: IPCOM000096448D
Original Publication Date: 1963-Jun-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 73K

Publishing Venue

IBM

Related People

Grubb, HR: AUTHOR

Abstract

In the shift register in A, bistable fluid logic devices are used as intermediate stage latches 10, 12 and 14 and main stage latches 11 and 13. With such, two successive fluid shift pulses SP1 and SP2 are required to shift information from one main stage to the next main stage.

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Fluid Logic Shift Register with Intermediate Stages

In the shift register in A, bistable fluid logic devices are used as intermediate stage latches 10, 12 and 14 and main stage latches 11 and 13. With such, two successive fluid shift pulses SP1 and SP2 are required to shift information from one main stage to the next main stage.

Thus, as shown in B and A, a reset pulse at time t1 is supplied via 15 to reset each latch 10, 12 and 14. At T2, while the gate and timing pulse TP are up, bits of information are entered in parallel into those selected ones of latches 10, 12 and 14 to which a bit pulse is provided. This is because when TP comes up at t2, TP and gate and bit pulses are three-way And'd by two sequential two-way And's 16 and 17.

Assuming that a bit is entered only in latch 12 to provide a 010 in the register, shift right pulse SR comes up at t3 to condition the register for shift right to the main stages. This shift begins when shift pulse SP2 comes up at t4. The off output from 10 is And'd with SP2 at 18 to supply a pulse to control port 19 to set latch 11 to off, if not already off. Meanwhile, the on output from 12 is And'd with SP2 at 20 to supply a pulse to control port 21 to set latch 13 on, if not already on.

At t5 when shift pulse SP1 comes up, the off output from 11 is transmitted via line 22 and And'd at 23 with SR to provide a signal that is And'd at 24 with SP1 to provide a pulse to 25. This pulse is Or'd through successive Or's 26 and 27 to provide a control pulse to switch the power stream in latch 12 to off. Also at t5 time, the on output from 13 is transmitted via line 28 and And'd at 29 w...