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Shift Sensitive Latch Circuit

IP.com Disclosure Number: IPCOM000096459D
Original Publication Date: 1963-Jun-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 29K

Publishing Venue

IBM

Related People

Heilwell, MF: AUTHOR

Abstract

The circuit employs And, Or and Invert logic circuits and operates as a normal set-reset latch. It is sensitive to the shifts of set and reset inputs so as to appear to have differentiating networks on each input.

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Shift Sensitive Latch Circuit

The circuit employs And, Or and Invert logic circuits and operates as a normal set-reset latch. It is sensitive to the shifts of set and reset inputs so as to appear to have differentiating networks on each input.

Two latches comprise the circuit. Latch 1 responds to the input which is first changed from its normal level and gates latch 2 accordingly. Latch 2 stores the data and is set or reset according to the state of latch 1.

The set and reset inputs are applied to each group of And's. Normally, the set input is at a down level and the reset input is at an up level. If the set input is raised, the circuit is set independently of the state of the reset input. If the reset input is lowered, the circuit is reset independently of the state of the set input. Lowering the set input or raising the reset input does not affect the state of the circuit.

The set and reset outputs are provided from the Invert circuits of the second group of logic circuits. The set output is at an up level when the circuit is set and down when the circuit is reset. The reset output is up when the circuit is reset and down when the circuit is set.

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