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Fast Recovery Signal Limiter for Sense Amplifier

IP.com Disclosure Number: IPCOM000096463D
Original Publication Date: 1963-Jun-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 23K

Publishing Venue

IBM

Related People

Foglia, HR: AUTHOR

Abstract

The fast-recovery signal limiter arrangement has a pair of semiconductor diodes 1 and 3 connected in back-to-back relationship and capacitively coupled between input terminal S and output terminal 7. A voltage source -V connected at junction 9 normally forwardly biases each diode 1 and 3. The signal limiter arrangement passes bipolar or unipolar pulses, respectively, when both or an appropriate one of diodes 1 and 3 exhibit slow recovery characteristics. Slow-recovery diodes exhibit a characteristic low reverse impedance subsequent to a period of forward conduction. This is due to the presence of free minority carriers in the base region which support a charge transfer phenomenon.

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Fast Recovery Signal Limiter for Sense Amplifier

The fast-recovery signal limiter arrangement has a pair of semiconductor diodes 1 and 3 connected in back-to-back relationship and capacitively coupled between input terminal S and output terminal 7. A voltage source -V connected at junction 9 normally forwardly biases each diode 1 and 3. The signal limiter arrangement passes bipolar or unipolar pulses, respectively, when both or an appropriate one of diodes 1 and 3 exhibit slow recovery characteristics. Slow- recovery diodes exhibit a characteristic low reverse impedance subsequent to a period of forward conduction. This is due to the presence of free minority carriers in the base region which support a charge transfer phenomenon.

When positive pulse 13 is applied at input terminal S, diode 1 is driven further into forward conduction and diode 3 is reversely biased. Accordingly, the energy levels in the base and anode regions of diode 3 are reversed and the flow of free minority carriers across the diode junction supports reverse current flow through it. Conversely, when negative pulse 13 is applied at input terminal S, diode 1 is reversely biased and conducts in the reverse direction and diode 3 is driven further into forward conduction.

When the magnitude of the quiescent bias current is determined such that the total charge stored by diodes 1 and 3 is at least equal to the total charge of input signals 11 and 13, respectively, output signals 11' and 13' at outp...