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A One Transistor, Two Core Per Bit Register

IP.com Disclosure Number: IPCOM000096470D
Original Publication Date: 1963-Jun-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Dickenson, WE: AUTHOR

Abstract

This is a parallel or serial readin, serial readout register. During readin, selected information cores ad clock core CC1 are set. During readout, the information cores are interrogated in sequence with reset pulses, a pulse appearing on the readout line for each one that is reset. In the upper drawing, the first clock pulse resets CC1, causing transistor T1 to saturate. T1 saturates quickly because winding Ta provides positive feedback. Winding Tb is a reset winding ad thus, if IC1 was set, a output pulse appears on the readout line. If IC1 was not set, no output pulse appears. Winding Tc is a set winding ad thus, the saturation current from T1 overrides the first clock pulse and sets CC2. The second clock pulse, in a similar manner, reads out IC2 and sets CC3. This continues until all information cores have been interrogated.

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A One Transistor, Two Core Per Bit Register

This is a parallel or serial readin, serial readout register. During readin, selected information cores ad clock core CC1 are set. During readout, the information cores are interrogated in sequence with reset pulses, a pulse appearing on the readout line for each one that is reset. In the upper drawing, the first clock pulse resets CC1, causing transistor T1 to saturate. T1 saturates quickly because winding Ta provides positive feedback. Winding Tb is a reset winding ad thus, if IC1 was set, a output pulse appears on the readout line. If IC1 was not set, no output pulse appears. Winding Tc is a set winding ad thus, the saturation current from T1 overrides the first clock pulse and sets CC2. The second clock pulse, in a similar manner, reads out IC2 and sets CC3. This continues until all information cores have been interrogated. The clock cores can be shared by additional information cores which can be connected in series as shown.

The lower drawing shows a register capable of simultaneous readin and readout. The readout portion is essentially the same as the register of the other drawing except that the clock ring is closed. The top row of cores comprises a serial readin ring. The information bit value controls the gates on the left. When the 1 gate is activated and a readin pulse occurs, one of the transistors sets an information core. If the 0 gate is activated instead, the information cores remain reset. This registe...