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Browse Prior Art Database

Information Checking System

IP.com Disclosure Number: IPCOM000096473D
Original Publication Date: 1963-Jun-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 54K

Publishing Venue

IBM

Related People

Propster, CH: AUTHOR

Abstract

In data transmission links having a fixed or even variable character length, parity bits have previously transmitted only at the expense of a longer character, having one bit more than the required data bits. Where the link requires each character to be preceded or ended by start or stop bits, parity information can be transmitted without an extra data bit and in less average time than the extra data bit would a require. Such is effected in this system by modulating the space between characters in a manner to represent parity information. unusual space bit length indicates even parity and the usual space bit length indicates odd parity.

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Information Checking System

In data transmission links having a fixed or even variable character length, parity bits have previously transmitted only at the expense of a longer character, having one bit more than the required data bits. Where the link requires each character to be preceded or ended by start or stop bits, parity information can be transmitted without an extra data bit and in less average time than the extra data bit would a require. Such is effected in this system by modulating the space between characters in a manner to represent parity information. unusual space bit length indicates even parity and the usual space bit length indicates odd parity.

Data to be transmitted is entered at input terminal 1 to input register 2 which has storage locations for five data bits and a parity bit. Terminal 1 is also connected to timer and control unit 3 and parity check unit 4. When all the bits for one character have been loaded into register 2, proper parity is verified by unit 4. If the data is valid, unit 3 provides a signal to start pulse generator 5 on line 6. When subsequent characters are presented, a start pulse is transmitted for all characters to convey parity for the preceding character. The unit stops after the start pulse, if an invalid character is sensed. Generator 5 produces a signal on line 7, the input to transmitter 8, which causes a start pulse to be transmitted over line 9.

Unit 3 then produces signals on lines 10 and 11. These operate to shift the data out of register 2 over line 12 through And 13 to line 7 to transmitter 8 and to enter new data into register 2 via terminal 1. At the conclusion of the character data bit transmission, unit 3 responds to a signal from unit 4 on line 14. Depending on the character, there is a signal on line 14 indicating an even or odd number of information bits.

If the system is to maintain odd parity and the number of bits is odd, unit 3 develops a signal on line 15 to character space generator 16. Transmitter 8 responds to the output of generator 16 by sending a space between characters equal to a usual or normal space bit time (one data bit time). In the event of an even number of bits, unit 3 develops a signal on line 17 to generator 18 which causes the transmitter to send a space bit of unusual time duration (two data bit times) between characters.

The transmitted signal on line 9 takes the form of signal 19. Each character is preceded by a start pulse one bit time long. The following five bit times are used to convey data. Where the system operates to maintain odd p...