Browse Prior Art Database

High Density Latch

IP.com Disclosure Number: IPCOM000096504D
Original Publication Date: 1963-Jun-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Grubb, HR: AUTHOR [+2]

Abstract

Drawings A and B show two latch arrangements. In A, a positive And 1 is coupled to the base of inverter T1. The collector of T1 and a Reset terminal are coupled to the base of inverter T2 by positive Or 2. Feedback from the collector of T2 to the base of T1 is provided by resistor R1. In addition, to providing feedback, R1 is the pulldown resistor for the And.

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High Density Latch

Drawings A and B show two latch arrangements. In A, a positive And 1 is coupled to the base of inverter T1. The collector of T1 and a Reset terminal are coupled to the base of inverter T2 by positive Or 2. Feedback from the collector of T2 to the base of T1 is provided by resistor R1. In addition, to providing feedback, R1 is the pulldown resistor for the And.

Positive inputs at 1 turn T1 on, and, assuming Reset is at the down level, T2 turns off. Positive feedback through R1 holds T1 on. A positive Reset potential turns T2 on, removing the feedback to T1 and turning the latter off.

Drawing B shows a similar, higher speed latch in which Or 2 is comprised of diodes and in which feedback is provided by diode D1.

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