Browse Prior Art Database

Binary Memory Array

IP.com Disclosure Number: IPCOM000096506D
Original Publication Date: 1963-Jun-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Narud, JA: AUTHOR [+2]

Abstract

The drawing shows one storage location of a memory array. Each storage location has a potential network having resistors R(1) and R(2) and a tunnel diode 5 connected between biased word and bit lines W and B and a reference potential. Junction 6 assumes two different values of potential depending on the conduction condition of tunnel diode 5.

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Binary Memory Array

The drawing shows one storage location of a memory array. Each storage location has a potential network having resistors R(1) and R(2) and a tunnel diode 5 connected between biased word and bit lines W and B and a reference potential. Junction 6 assumes two different values of potential depending on the conduction condition of tunnel diode 5.

Diode 5 is brought to the selected one of its two conducting conditions by pulsing one or both of lines W and B. Junction 6 is connected to sense line S through a semiconducting diode 7. When the diode 5 is in its high voltage condition, diode 7 offers a low impedance. When diode 5 is in its low voltage condition, diode 7 offers a substantially higher impedance.

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