Browse Prior Art Database

Computer System

IP.com Disclosure Number: IPCOM000096552D
Original Publication Date: 1963-Jul-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Haynes, MK: AUTHOR

Abstract

This computer system is organized to reduce memory access time, and also to reduce the number of times information must be put in and taken out of memory in order to process data. The system includes a plurality of memory units 1, 2 and 3 which have independent access channels. A plurality of arithmetic units 4, 5 and 6 each perform different logical operations. Interconnections are made between the memories and arithmetic units through the switching center 7.

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Computer System

This computer system is organized to reduce memory access time, and also to reduce the number of times information must be put in and taken out of memory in order to process data. The system includes a plurality of memory units 1, 2 and 3 which have independent access channels. A plurality of arithmetic units 4, 5 and 6 each perform different logical operations. Interconnections are made between the memories and arithmetic units through the switching center 7.

In operation, program instructions are fed to control unit 8. This scans a group of program instructions and sets up the interconnections in the switching center. The interconnections are set up so that a stream of data is taken from any one of the memories and processed through one or more of the arithmetic units before being returned to one of the memories.

By careful selection of the interconnections, streams of data are taken from the memories and processed through the arithmetic units simultaneously. This relieves the congestion created in a single memory system. Also, the number of times access must be made to the memory is cut down by processing the data through a number of arithmetic units before returning the data to the memory.

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