Browse Prior Art Database

Delay Line Memory

IP.com Disclosure Number: IPCOM000096571D
Original Publication Date: 1963-Jul-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Pricer, WD: AUTHOR

Abstract

This memory element uses a transistor-delay line oscillator for the storage of information. Transistor 10 has delay line 12 connected between its collector and base electrodes. The collector and emitter of transistor 10 are respectively connected through resistors to terminals 14 and 16 where biasing potentials are applied. Diode 18 is for writing into and reading from the memory element. To terminal 20 are applied signals for synchronizing the stored information.

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Delay Line Memory

This memory element uses a transistor-delay line oscillator for the storage of information. Transistor 10 has delay line 12 connected between its collector and base electrodes. The collector and emitter of transistor 10 are respectively connected through resistors to terminals 14 and 16 where biasing potentials are applied. Diode 18 is for writing into and reading from the memory element. To terminal 20 are applied signals for synchronizing the stored information.

When potentials are first applied via terminals 14 and 16, transistor 10 immediately begins to oscillate, e. g., for a half cycle it is conductive and for the other half cycle, nonconductive (waveform 25). Any information inserted into the memory element is inverted by transistor 10 and fed back around delay line 12 (waveform 27). When it is desired to read the information on delay line 12, the potentials applied to terminals 14 and 16 are simultaneously raised. The voltage at the anode 19 of diode 18 is lowered by placing a negative potential on terminal 22 as shown at point 26 on waveform 28. By this action, transistor 10 is forced out of conduction and diode 18 becomes forwardly biased so that any data on delay line 12 is allowed to pass to terminal 22. Upon transistor 10 becoming nonconductive, a positive level shift occurs at its collector, e. g., waveform 29, and is inserted onto delay line 12.

To write information onto delay line 12, diode 18 is next returned to its nonconductiv...