Browse Prior Art Database

Integrated Shift Cell

IP.com Disclosure Number: IPCOM000096573D
Original Publication Date: 1963-Jul-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 46K

Publishing Venue

IBM

Related People

DeWitt, D: AUTHOR [+2]

Abstract

This shift cell has flexibility of shift patterns and ease of fabrication. The circuit configuration reduces the amount of drive current required for a shift operation.

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Integrated Shift Cell

This shift cell has flexibility of shift patterns and ease of fabrication. The circuit configuration reduces the amount of drive current required for a shift operation.

TL is a latch transistor, typically a four-layer high alpha thyratron structure, fabricated with an integral bilateral gate transistor TG. Shifting source 20 is connected through impedance elements to the base of transistor TG. Data is supplied to a shift cell at terminal A. This is connected to the common emitter region between transistors TG and TL. The common emitter region is connected to a current supply including resistor R1 and a source of suitable voltage depending upon the conductivity of the common emitter region. The collector of TL is connected to a voltage supply of suitable polarity by way of load resistor R3. Feedback path 21 including a resistor R2 interconnects the collector electrode and the common emitter region. The base of TL is connected to a source of reference potential. Resistors R4, R5 and capacitor C1 form a level shifting and temporary storage network at the output of TL, designated as terminal B.

When TL is turned on, by an input pulse at terminal A or the output from the preceding stage, the collector is near ground potential and little or no current flows in the feedback circuit. Negative current flows into the emitter from R1 holding TL on. When TL is turned off by a suitable input, the collector electrode rises toward the supply voltage and positive current flows in the feedback circuit to overcome the negative current from R1 holding TL off. The high input impedance of the input circuit decreases the drive current requirements for circuit operation. Resistors R4 and R5 are selected so that the non-grounded terminal of capacitor C1 is positive when TL is off and negative when TL is on. A shift pulse at source 20 momentarily turns TG on to deliver a pulse of current from capacitor C1 to the gate transistor of the next stage. The current delivered is of the polarity to set the next stage TL to the state previously held by the preceding TL. Although the preceding TL might be simultaneously shifting its state, R4, R5 and C1 have a time constant long enough so that the shift pulse is concluded before the new state of the preceding TL has contributed a significant charge to C1.

More than one gate transistor TG can be used per latch transistor TL to produce various patterns of switching. Thus, with two gates per latch, it...