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Delay Line Implementation of Linear Shift Register Circuits

IP.com Disclosure Number: IPCOM000096605D
Original Publication Date: 1963-Aug-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 53K

Publishing Venue

IBM

Related People

Daykin, DR: AUTHOR

Abstract

The number system here used is binary and serial. Thus, in a binary series A(0)x/0/+A(1)x/1/+A(2)x/2/..... the presence in time of a pulse in a series of pulses determines the existence of a digit in a given order. Further, for this, high order bits are considered to be first in time. Multiplication and division, as described, are binary without carry or correction and error detection codes.

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Delay Line Implementation of Linear Shift Register Circuits

The number system here used is binary and serial. Thus, in a binary series A(0)x/0/+A(1)x/1/+A(2)x/2/..... the presence in time of a pulse in a series of
pulses determines the existence of a digit in a given order. Further, for this, high order bits are considered to be first in time. Multiplication and division, as described, are binary without carry or correction and error detection codes.

In the delay line multiplier in A, a delay line 10 of delay K-1 bits is used with a circuit clock cycle of K bits. Normal regeneration is by means of And 11, delay 1 bit circuit 12, Or 13, and Exclusive Or 14. Exclusive Or 14 provides an output for one input and not the other, but no output for both inputs or not either input. When multiplying, And 17 is enabled at time TK-T2 time to provide a denominational shift in the multiplicand for each denominational order of the multiplier greater than unity. The terms of the multiplier are entered through And
18. The presence or absence of these terms at the proper times is used to select the terms of the multiplicand or not for recirculation. After recirculation for as many cycles as there are orders of the multiplier, the number being recirculated is the product of multiplier and multiplicand with no carry being effected.

In the delay line divider in B, an Exclusive Or 22 is shown as a single logic block with three inputs. Only two of these are used at one time. After the d...