Browse Prior Art Database

Selective Masking and Prevention of Surface Microalloying

IP.com Disclosure Number: IPCOM000096632D
Original Publication Date: 1963-Sep-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Hess, MS: AUTHOR

Abstract

In the fabrication of semiconductor devices, silicon is vacuum deposited for impurity diffusion masking. Also, silicon monoxide is vacuum deposited to prevent microalloying during the controlled vapor diffusion of desired impurities.

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Selective Masking and Prevention of Surface Microalloying

In the fabrication of semiconductor devices, silicon is vacuum deposited for impurity diffusion masking. Also, silicon monoxide is vacuum deposited to prevent microalloying during the controlled vapor diffusion of desired impurities.

A semiconductor wafer 2 is first selectively covered with silicon 4. The silicon is derived from an electron bombardment evaporation source and serves to mask and inhibit the movement of impurities through it. A thin film of silicon monoxide 6 is then deposited over silicon mask 4. Following this, the wafer is exposed to an impurity vapor such as gallium 8. Owing to the presence of silicon monoxide, the gallium does not directly impinge upon surface 10 of semiconductor wafer 2. Instead, it hits the silicon monoxide layer 6 first and then diffuses through the silicon monoxide into wafer 2. The presence of the silicon monoxide prevents direct impingement of the gallium with the wafer, preventing microalloying and galling of the water surface.

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