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Slow Add Cycle for Magnetic Drum

IP.com Disclosure Number: IPCOM000096651D
Original Publication Date: 1963-Sep-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

West, LE: AUTHOR [+2]

Abstract

The circuit enables entry of numeric digits onto a magnetic drum in a high-order-first sequence and arithmetic operations involving the same numeric digits in a low-order-first sequence. In the circular timing diagram, upper right, each track on drum 1 is indicated as being divided into eleven digit segments respectively designated Sign, 10/9/...10/0/. It is assumed that arithmetic operations involve tracks 2 and 3 on drum 1. Digits are read alternately from each of the tracks 2 and 3 to an adder 4. The sum is written back into either one of the tracks 2 or 3, as selected.

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Slow Add Cycle for Magnetic Drum

The circuit enables entry of numeric digits onto a magnetic drum in a high- order-first sequence and arithmetic operations involving the same numeric digits in a low-order-first sequence. In the circular timing diagram, upper right, each track on drum 1 is indicated as being divided into eleven digit segments respectively designated Sign, 10/9/...10/0/. It is assumed that arithmetic operations involve tracks 2 and 3 on drum 1. Digits are read alternately from each of the tracks 2 and 3 to an adder 4. The sum is written back into either one of the tracks 2 or 3, as selected.

Associated with track 2 is a read head 1 and a write head 1. Associated with track 3 is a read head 2 and a write head 2. Read head 2 is positioned in such a manner that it reads a particular digit segment one digit interval later than read head 1. Write head 1 and write head 2 are positioned in a corresponding location one digit interval later than read head 2.

D-Counter 5 controls the reading and writing of digits. Normally, counter 5 is reset upon each revolution of drum. 1 by a word timing pulse from track 6 on line
7. If a control signal is supplied on line 8, however, counter 5 is stepped in a regular manner under control of digit timing pulses from track 9 of drum 1. The reset pulse on line 7 is ineffective. Counter 5 counts once for each digit interval up to a total which is one less than the total number of digit segments on drum 1. In this case, the maximum count for counter 5 is ten. Digits read by read head 1 in track 2 are gated through gate 10 at D(9) time which represents a counter 5 count of nine. Digits read from track 3 by read head 2 are gated through gate 11 ...