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Binary Adder

IP.com Disclosure Number: IPCOM000096652D
Original Publication Date: 1963-Sep-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 3 page(s) / 53K

Publishing Venue

IBM

Related People

Willette, EL: AUTHOR [+3]

Abstract

This is a binary adder which, in addition to utilizing carry ripple, has a carry look-ahead circuit. This insures that all carries arrive at their respective bit positions no later than three circuit levels of delay after the receipt of all operands.

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Binary Adder

This is a binary adder which, in addition to utilizing carry ripple, has a carry look-ahead circuit. This insures that all carries arrive at their respective bit positions no later than three circuit levels of delay after the receipt of all operands.

Each bit position of the binary adder has a binary full adder circuit 2 which accepts A and B operands and an input carry Cin and provides both sum S and carry C outputs. Also in each bit position is Or 4. Its output is indicative of a carry propagate function Cp, that is, the condition where a carry into an adder position automatically propagates through the position due to the presence of one of the operands. Also in each adder bit position is optional majority circuit 6. This generates a carry bit that is independent of the carry bit produced by circuit
2.

In each circuit 2, two circuit levels of the delay are required after the receipt of the operands to generate a sum bit. Only a single circuit level of delay is required for the generation of a carry bit. Bit positions 0... 2 make up Group I of the adder circuit. They require no look-ahead circuitry, since the carry into position 2 occurs no later than three circuit levels after a carry into position 0. Considering the bit positions of Group II and the single bit position 7 of Group III, however, carry look-ahead circuitry meets the three circuit level delay requirement. Additionally, intra-group look-ahead carries into bit positions 5 and 6 are also required to satisfy this criteria.

The carry look-ahead circuit is shown beneath the adder and has three main groups of circuits. And's 10, 12 and 14 and Or 16 are the circuitry for generating look-ahead Group I carry. And's 18, 20 and 22 are the circuitry for generating the look-ahead carries into bit positions 6 and 5. And's 24, 26 and 28 and Or 30 are the circuitry for generating...