Browse Prior Art Database

Data Transfer Matrix

IP.com Disclosure Number: IPCOM000096657D
Original Publication Date: 1963-Sep-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Schroeder, EN: AUTHOR

Abstract

The left-hand drawing shows a circuit to transfer data from a plurality of data carrying lines to a plurality of data reception locations. Transistor switches S connecting the input and output lines are selectively activated under the control of a programmed switch control.

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Data Transfer Matrix

The left-hand drawing shows a circuit to transfer data from a plurality of data carrying lines to a plurality of data reception locations. Transistor switches S connecting the input and output lines are selectively activated under the control of a programmed switch control.

The switches transfer signals from the data carrying line connected to the switch to the data reception line connected to the switch. The program used is versatile and is limited only by the requirement that two data signals cannot appear on a single data reception line at the same time.

The right-hand drawing shows the switch which is used. Data on the data carrying line appears as a positive pulse at the base of a first transistor. The switch is not opened, however, unless a second transistor also receives a positive pulse from the programmed switch control. Since both transistors are in series in emitter follower configuration, a current multiplication occurs with power supplied by the collector source + V.

Each data reception location can be a single memory or a plurality of memories gated open in parallel or in time sequence. Residual potentials caused by high currents in the data reception lines can be shunted to ground at preselected times. All gating and shunting is accomplished by activating a single or a plurality of transistors in a manner similar to that illustrated in the right-hand drawing.

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