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Connective Register Using Majority Logic

IP.com Disclosure Number: IPCOM000096669D
Original Publication Date: 1963-Sep-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Smith, MG: AUTHOR [+2]

Abstract

This logical circuit generates any one of the sixteen possible logical connectives for two binary numbers A and B. Seven majority logic blocks M1... M7 are interconnected as shown. Each majority logic block produces an output whenever two or more of the three inputs are present.

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Connective Register Using Majority Logic

This logical circuit generates any one of the sixteen possible logical connectives for two binary numbers A and B. Seven majority logic blocks M1... M7 are interconnected as shown. Each majority logic block produces an output whenever two or more of the three inputs are present.

The particular logical function to be generated by the circuit is selected by applying control signals to terminals C1... C4. The table indicates which control signals are applied in order to generate any one of the logical functions.

For example, if the logical And function is to be generated, control terminal C1 is activated. When C1 is activated a signal appears on the output terminal only when both A and B are present. For this input condition, i. e., C1, A, and B present, majority circuits M1 and M2 are activated. M1 and M2 supply two inputs to M5.

The third input to M5 is permanently absent (0), causing M5 to perform as an And. The output from M5 is applied to M7 which receives a constant signal (1) on one of its three inputs. Therefore, M7 acts as an Or, producing an output signal whenever M5 or M6 are activated.

For this example, with C1 activated, if either A or B are absent no output is produced from M7.

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