Browse Prior Art Database

Telegraph Synchronizer

IP.com Disclosure Number: IPCOM000096695D
Original Publication Date: 1963-Sep-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Oeters, HR: AUTHOR [+2]

Abstract

This circuit maintains synchronization between incoming telegraph signals and a data processing system.

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Telegraph Synchronizer

This circuit maintains synchronization between incoming telegraph signals and a data processing system.

Start stop synchronization can be maintained even though the data processing system receives, scans, signals only intermittently. Asynchronous, start stop, characters serially received on an incoming line are regularly sampled for subsequent transfer to the data processing system DPS. Clock signals repeatedly step a sample counter SC from one to fifteen and back to one again. Normally SC is, regardless of its current position, reset to nine when a stop to start transition is detected on the incoming line. Since the interval between samples of the stop and start bits can be less than the scan rate of the DPS, the DPS may miss the stop bit and lose character synchronization. The circuit compensates for this situation. Delay (D), and (&), Invert (I) and Exclusive Or (XOR) logic circuits are labeled.

The stop bit, though properly sampled, may be missed by the DPS. Normally, each incoming bit is sampled when SC equals one, while count nine coincides with the end of the sampled bit. SC is reset to nine at the stop to start transition, reducing the interval between sampling of the stop bit and the start bit, if SC is out of synchronism, as shown. In this case, however, DPS misses the stop bit because, by regularly scanning sampled bits, its ready times bridge the sampling of the stop bit and the start bit. Cumulative drift causes sampling of the...