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Serial Parallel DR Tunnel Diode Memory

IP.com Disclosure Number: IPCOM000096708D
Original Publication Date: 1963-Sep-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Stuckert, PE: AUTHOR

Abstract

The destructive read tunnel diode memory in A has a plurality of word drive lines w and bit drive lines b. These are arranged in coordinate fashion and connected at each crossover point by a memory cell c. Each cell c has tunnel diode 1 connected to bit drive line b along resistor 3 and to word drive line w along resistor 5 and backward coupler 7. In an alternate form, coupler 7 can be replaced by a loosely coupled or differentiating transformer. The junction of diode 1 and resistors 3 and 5 is connected through semiconductor coupling diode 9 to sense line s.

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Serial Parallel DR Tunnel Diode Memory

The destructive read tunnel diode memory in A has a plurality of word drive lines w and bit drive lines b. These are arranged in coordinate fashion and connected at each crossover point by a memory cell c. Each cell c has tunnel diode 1 connected to bit drive line b along resistor 3 and to word drive line w along resistor 5 and backward coupler 7. In an alternate form, coupler 7 can be replaced by a loosely coupled or differentiating transformer. The junction of diode 1 and resistors 3 and 5 is connected through semiconductor coupling diode 9 to sense line s.

The operation of the memory of A during read and write operations is illustrated in B and C. In B, curve x is the characteristic curve of diode 1. Curve y is the characteristic curve of diode 9. Curve z is the composite characteristic of diodes 1 and 9 in parallel. The pulse sequences for effecting read and write operations are illustrated in C.

The quiescent 0 and 1 operating states of memory cell c are defined by the intersection of load line 11 with composite curve z. To effect readout, a selected word drive line w is energized positive by drive pulse 13. During the rise time t(0)-t(1) of pulse 13, positive pulse 15 is delivered by coupler 7 and applied across diode 1 along resistor 5 so that load line 11 is raised to 11'. When interrogated memory cell c is in a 1 state, diode 1 is switched to the high voltage portion of composite curve z. At this time, change in con...