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Increasing the Speed of NPC Circuits

IP.com Disclosure Number: IPCOM000096711D
Original Publication Date: 1963-Sep-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Corradetti, M: AUTHOR

Abstract

The operating speed of neon photoconductor circuits is limited primarily by the long decay times of the photosemiconductors, which exceed the response times by almost an order of magnitude. In order to increase the speed of operation of NPC networks, successive stages I... VI, are alternately and cyclically reset. This is by turning off the voltages as shown in the timing diagram such that the decay times are rendered largely ineffective. Without employing this procedure, the luminescence of the neon lamp in stage II would, e. g., be undesirably prolonged due to the long decay time of the photosemiconductor in stage I. That prolongation propagates and accumulates through all stages.

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Increasing the Speed of NPC Circuits

The operating speed of neon photoconductor circuits is limited primarily by the long decay times of the photosemiconductors, which exceed the response times by almost an order of magnitude. In order to increase the speed of operation of NPC networks, successive stages I... VI, are alternately and cyclically reset. This is by turning off the voltages as shown in the timing diagram such that the decay times are rendered largely ineffective. Without employing this procedure, the luminescence of the neon lamp in stage II would, e. g., be undesirably prolonged due to the long decay time of the photosemiconductor in stage I. That prolongation propagates and accumulates through all stages.

By turning off successive stages alternately and cyclically, the luminescence of the neon lamp of stage II is, e. g., suppressed prior to the end of the decay time of the photosemiconductor of stage I. In this manner, it is possible to save for each stage up to 50 percent of the time that has been previously required.

The method of cyclically and alternately turning off the voltages in successive stages is used in an adder. This has a matrix 11 for evennumbered and a matrix 10 for odd-numbered storage locations. The even numbered storage locations of storage units 5 and 6 are read into adder matrix 11 at the time of phase 2. The odd numbered storage locations of those storage units are read into adder matrix 10 at the time of phase 1 and read out i...