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Generating and Processing an Error Character

IP.com Disclosure Number: IPCOM000096755D
Original Publication Date: 1963-Oct-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Mullery, AP: AUTHOR [+3]

Abstract

The system is for use with a high to low order arithmetic process unit. It has special controls for detecting an error, generating a special character for insertion into the output data flow and still continue a given operation otherwise normally. Process unit 10 actually performs arithmetic operations on operands coming in on channels A and B. The output of unit 10 is fed through gate 12 and into buffer 14. Here it is stored temporarily until a subsequent cycle and thence through gate 16 into buffer 18 and depending upon the nines complement indications for a given operation out through complementing block 20 in through decoder 22. Here the output is converted into a standard four-bit binary code for subsequent use in the system.

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Generating and Processing an Error Character

The system is for use with a high to low order arithmetic process unit. It has special controls for detecting an error, generating a special character for insertion into the output data flow and still continue a given operation otherwise normally. Process unit 10 actually performs arithmetic operations on operands coming in on channels A and B. The output of unit 10 is fed through gate 12 and into buffer
14. Here it is stored temporarily until a subsequent cycle and thence through gate 16 into buffer 18 and depending upon the nines complement indications for a given operation out through complementing block 20 in through decoder 22. Here the output is converted into a standard four-bit binary code for subsequent use in the system.

The system anticipates that the error is detected in a character actually transmitted over channels A or B which are done in the error character detection blocks 24 and 26. Similarly, an error is detected in unit 10, in which event, an output on line 28 is provided. An error signal emanating from blocks 24, 26 or line 28 is fed to inhibit block 30. This prevents the instantaneous output from unit 10 from ever reaching the buffer 14. At the same time, the error signal is introduced into the bottom of buffer 14 on line 32 which, in effect, stores an error signal in buffer 14. The error signal is later passed through gate 16 to buffer 18 and through complementing block 20 and thence into output...