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Three Input Binary Adder

IP.com Disclosure Number: IPCOM000096790D
Original Publication Date: 1963-Nov-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 4 page(s) / 146K

Publishing Venue

IBM

Related People

Geller, AR: AUTHOR

Abstract

Three operands are added by this simultaneous carry binary adder.

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Three Input Binary Adder

Three operands are added by this simultaneous carry binary adder.

Three 27 bit operands X, Y and Z plus two input carries C1SO and C2SO are added to form a 27-bit sum S. The addition is performed in three sections each having three 3 bit groups, all carries between sections (C1S, C2S), between groups (C1G, C2G) and between bits (C1B, C2B) being generated simultaneously. These carries, together with halfsum information H, are simultaneously supplied to standard half adder logic which forms the final sum. The half sums H are derived by bit function logic. Additional functions used to generate carries are derived by this logic and by group function and section function logic. Section, group and bit carry logic utilizes the function logic outputs to supply bit, group and section carries to the adder logic.

Equations defining the function logic shown in the drawings are given for any bit, group or section n as follows: Bit Function Logic
Dn = XnYn + YnZn + XnZn
Hn = Xn XOR Yn XOR Zn
Vn = XnYnZn
Tn=Xn+Yn+Zn
Group Function Logic
DGn = D(n+2) + T (n+2)*D(n+1) + T(n+2)*T(n+1)* Dn+V(n+1)* Dn EGn = T(n+2)* T(n+1)+T(n+2)*Dn + V (n+1) + D (n+1)*Dn FGn = V(n+2)* Dn + V(n+2)* T(n+1) + D(n+2)* V(n+1)+ D(n+2)* D(n+1)* Dn

GGn= V(n+2)* D(n+1)+ V (n+2)*T(n+1)*Dn + D(n+2)*V(n+1)* Dn TGn = T(n+2)*T(n+1)*Tn + T(n+2)*Vn + V(n+1)*Tn + D(n+1)*Vn VGn= V(n+2)*Vn + V(n+2)*T(n+1)*Tn + D(n+2)*V(n+1)*Tn + D(n+2) * D(n+1)* Vn

Section Function Logic

DSn = DG(n+2) + TG(n+2)* DG(n+1) + TG(n+2)* TG(n+1)* DGn + TG(n+2)* EG(n+1)* GGn + EG(n+2)* GG(n+1)

+ EG(n+2)* VG(n+1)* DGn + EG(n+2)* FG(n+1)* GGn

ESn = TG(n+2)* TG(n+1)* EGn + TG(n+2)* EG(n+1)* FGn + EG(n+2)* VG(n+1)* EGn...