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Common Bit Sense Line Circuit

IP.com Disclosure Number: IPCOM000096796D
Original Publication Date: 1963-Nov-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Kohn, G: AUTHOR [+2]

Abstract

The circuit is for isolating bit signals from the sense amplifiers of a magnetic memory using a common bit sense line.

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Common Bit Sense Line Circuit

The circuit is for isolating bit signals from the sense amplifiers of a magnetic memory using a common bit sense line.

Bit signals applied to terminal 2 pass through preamplifier 4 and line 6 to amplifier 8 and to delay 10 in strobe gate 12. Bit signals out of amplifier 8 are applied through line 14 to a center tap on the transformer 16 primary. One end of transformer 16 primary connects to common bit sense line 18 of a magnetic memory. The other end connects through dummy load 20 to ground. A second common bit sense line for the other half of the memory can be substituted for load 20. The transformer 16 secondary connects through preamplifier 22 to the differential transformer 24 primary in strobe 12. Ends of transformer 24 secondary connect through diodes 26 and 28 to the ends of transformer 30 primary. The output from delay 10 connects to a center tap of this primary. The transformer 30 secondary connects as an input to sense amplifier 32.

A bit signal applied to terminal 2 passes through amplifier 4, line 6, amplifier 8, and line 14 to the center tap of 16. Load 20 is matched to line 18. Current applied to the center tap divides equally between these two loads. This causes signals of equal amplitude and opposite polarity to be induced in the transformer 16 secondary. These signals cancel in the transformer 16 secondary, preventing any bit signal from being applied to amplifiers 22 and 32.

To protect against bit noise being induce...