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High Speed Multiplier

IP.com Disclosure Number: IPCOM000096810D
Original Publication Date: 1963-Dec-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Haynes, MK: AUTHOR

Abstract

The drawing shows two stages of a high speed, carry save multiplier circuit using adders. These generate a carry output in one unit of time, a sum output in two units of time, and have a recycle period for their logical elements of four units of time.

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High Speed Multiplier

The drawing shows two stages of a high speed, carry save multiplier circuit using adders. These generate a carry output in one unit of time, a sum output in two units of time, and have a recycle period for their logical elements of four units of time.

Each stage of the circuit consists of a four-stage shift register 2, in which the bit of the multiplicand for that stage circulates, two And's 4 and 6, two adders 8 and 10, and two one phase delays 12 and 14. The lowest order bit of the multiplicand circulates in shift register 2a; the next lowest order bit of the multiplicand in shift register 2b. At phase two time, the lowest order bit of the multiplier is applied by line 16 to one input of And's 6. The other input to each And 6 is the phase two output from the corresponding shift register 2. Output line 18 from And 6 is connected as one input to adder 10. At phase four time, the next to the least significant bit of the multiplier is applied through line 20 to one input of And's 4.

The other input to each of And's 4 is the phase four output from the corresponding shift register 2. Output line 22 from And 4 is connected as one input to adder 8. One phase time after an input is applied to adder 10, the adder generates a carry output on line 24. This is connected through one phase delay 14 and line 26 to one input of adder 8.

One phase time after an input is applied to adder 8, the adder generates a carry output on line 28. Such is connected thr...