Browse Prior Art Database

Timing Circuit

IP.com Disclosure Number: IPCOM000096830D
Original Publication Date: 1963-Dec-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 28K

Publishing Venue

IBM

Related People

Hines, HW: AUTHOR [+2]

Abstract

This timing circuit produces long time delays in response to a very short initial pulse.

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Timing Circuit

This timing circuit produces long time delays in response to a very short initial pulse.

With switch 1 positioned as shown, capacitor 2 charges from source B+ via resistor 3 and high-impedance transistor 4 is on. Current flows from B+ via resistor 5 and the now forwardly biased diode 6 to keep transistor 7 off. Diode 8 prevents too much back bias on 4.

To initiate a timing period, 1 is actuated to connect 2 to negative source B-. This discharges 2 and turns 4 off. Threshold diode 6 now becomes reversely biased, creating a high emitter circuit impedance that reduces the emitter current to substantially zero. transistor 7 is now turned on by current supplied to its base from B- via resistor 9. This causes current flow from ground to B- via resistor 10 and produces an output signal at 11. Clamping diode 12 prevents the base of 7 from going above ground.

When 1 is returned to its shown position, 2 recharges toward the return voltage B+ of 3. The time constant of this timing network consists substantially of the RC network 3 and 2. When 2 becomes charged a sufficient degree, 4 turns on and 6 forward biases. This allows emitter current in 4 to flow and thus return the circuit to its initial state in which 4 is on and 7 is off.

The time delay provided by this circuit extends from the instant 1 is restored to its disconnected position until 7 turns off.

Timeout of the circuit can be stopped at any time by actuating 1 to connect 2 to B+. This provides a fas...