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Group Assembler/Disassembler

IP.com Disclosure Number: IPCOM000096833D
Original Publication Date: 1963-Dec-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Schellenberg, AG: AUTHOR

Abstract

The upper drawing shows the general system. It has five input lines 1...5, scanner 6 and assembler 7. The logical circuitry in assembler 7 is in the middle drawing.

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Group Assembler/Disassembler

The upper drawing shows the general system. It has five input lines 1...5, scanner 6 and assembler 7. The logical circuitry in assembler 7 is in the middle drawing.

Signals arrive onlines 1...5. These are periodically and sequentially sampled by scanner 6 and supplied to the input of assembler 7. The signals at the assembler 7 input, as shown in the bottom drawing, consist of a sample from line 1, followed by a sample from line 2, etc. The signal at the output of the assembler 7 is also shown. The output signal consists of three samples from line 3, followed by three samples from line 1, followed by three samples from line 4, etc.

Assembler 7 consists of four And's 8...11, two Or's 12 and 13, delay circuit 14 and timer 15. This has three outputs E1, E2 and E3. These are sequentially activated, one each time a bit arrives at the assembler 7 input.

Timer 15 is advanced one position each time a signal occurs on the assembler 7 input. In certain cases, timer 15 may, in fact, be advanced by the arrival of each bit at the assembler 7 input. In the particular example, the only output from timer 15, which is used by the circuitry, is the third output. Delay 14 is a storage which stores four bits of information. The logic which is shown provides the necessary rearrangement of input bits with a minimum amount of storage.

In the example, delay 14 provides four bits of storage. In the general case, the number of bits of storage needed is:

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