Browse Prior Art Database

Integrating Pulse Shaper With Hysteresis

IP.com Disclosure Number: IPCOM000096839D
Original Publication Date: 1963-Dec-01
Included in the Prior Art Database: 2005-Mar-07
Document File: 2 page(s) / 32K

Publishing Venue

IBM

Related People

Clapper, GL: AUTHOR

Abstract

This pulse shaping circuit combines the feature of active integration with hysteresis.

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Integrating Pulse Shaper With Hysteresis

This pulse shaping circuit combines the feature of active integration with hysteresis.

In U. S. Patent No. 2, 864, 007, hysteresis is employed in connection with a trigger circuit in which the integration is merely incidental and no active integration is performed. In U. S. Patent No. 3, 098, 939, active integration with feedback is used in combination with a pulse shaping circuit which lacks hysteresis characteristics.

The integrating pulse shaping circuit A combines active integration with hysteresis characteristics shown in B. The integrating pulse shaping circuit has transistors x1 and x2, integrating feedback loop L1, positive feedback loop L2 and a bypassing 10K resistor. This, in concert with loop L2, provides the hysteresis action to the input. With the input and output at -12 V, X1 and X2 are nonconductive. As such, junctions E, C and D are held to -12 V, -12 V and +6 V, respectively. As the input is slowly raised to -6 V, point C is held at a voltage more negative than -6 V.

This is because of current flow through the 10K resistor and through the loop path connected to the output, which is at -12 V. Raising the input voltage from -6 V to -4 V results in conduction through X1.

As a consequence, junction D, by virtue of loop L1, slowly lowers in potential until a value of below ground potential is reached. Then, transistor X2 is set into conduction to cause the output to rise, this being the on condition of the cir...